circuit MYFIFO :
  module MYFIFO :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip memData : UInt<512>, flip memValid : UInt<1>, flip advance_fifo : UInt<1>, tile : UInt, ready : UInt<1>, full : UInt<1>}

    reg state : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MYFIFO.scala 33:28]
    reg startup : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MYFIFO.scala 34:30]
    startup <= UInt<1>("h1") @[MYFIFO.scala 34:30]
    wire _topBuf_WIRE : UInt<512>[1] @[MYFIFO.scala 38:37]
    _topBuf_WIRE[0] <= UInt<512>("h0") @[MYFIFO.scala 38:37]
    reg topBuf : UInt<512>[1], clock with :
      reset => (reset, _topBuf_WIRE) @[MYFIFO.scala 38:29]
    reg droptile : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MYFIFO.scala 41:31]
    wire clearDrop : UInt<1>
    clearDrop <= UInt<1>("h0")
    when io.advance_fifo : @[MYFIFO.scala 44:30]
      droptile <= UInt<1>("h1") @[MYFIFO.scala 45:26]
    else :
      when clearDrop : @[MYFIFO.scala 46:32]
        droptile <= UInt<1>("h0") @[MYFIFO.scala 47:26]
    when io.memValid : @[MYFIFO.scala 51:26]
      node _T = lt(state, UInt<1>("h0")) @[MYFIFO.scala 52:27]
      when _T : @[MYFIFO.scala 52:41]
        node _state_T = add(state, UInt<1>("h1")) @[MYFIFO.scala 53:40]
        node _state_T_1 = tail(_state_T, 1) @[MYFIFO.scala 53:40]
        state <= _state_T_1 @[MYFIFO.scala 53:31]
      else :
        state <= UInt<1>("h0") @[MYFIFO.scala 55:31]
      topBuf[UInt<1>("h0")] <= io.memData @[MYFIFO.scala 58:31]
    reg full : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MYFIFO.scala 62:27]
    wire clearTop : UInt<1>
    clearTop <= UInt<1>("h0")
    node _T_1 = eq(state, UInt<1>("h0")) @[MYFIFO.scala 64:35]
    node _T_2 = and(io.memValid, _T_1) @[MYFIFO.scala 64:26]
    when _T_2 : @[MYFIFO.scala 64:52]
      full <= UInt<1>("h1") @[MYFIFO.scala 65:22]
    else :
      when clearTop : @[MYFIFO.scala 66:31]
        full <= UInt<1>("h0") @[MYFIFO.scala 67:22]
    reg buf2 : UInt<72>, clock with :
      reset => (reset, UInt<72>("h0")) @[MYFIFO.scala 71:27]
    reg buf3 : UInt<72>, clock with :
      reset => (reset, UInt<72>("h0")) @[MYFIFO.scala 72:27]
    reg buf4 : UInt<72>, clock with :
      reset => (reset, UInt<72>("h0")) @[MYFIFO.scala 73:27]
    reg empty2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h1")) @[MYFIFO.scala 75:29]
    reg empty3 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h1")) @[MYFIFO.scala 76:29]
    reg empty4 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h1")) @[MYFIFO.scala 77:29]
    node _T_3 = not(startup) @[MYFIFO.scala 79:14]
    when _T_3 : @[MYFIFO.scala 79:23]
      empty2 <= UInt<1>("h1") @[MYFIFO.scala 80:24]
      empty3 <= UInt<1>("h1") @[MYFIFO.scala 81:24]
      empty4 <= UInt<1>("h1") @[MYFIFO.scala 82:24]
    else :
      node _T_4 = and(full, empty2) @[MYFIFO.scala 83:26]
      when _T_4 : @[MYFIFO.scala 83:37]
        buf2 <= topBuf[0] @[MYFIFO.scala 84:22]
        clearTop <= UInt<1>("h1") @[MYFIFO.scala 85:26]
        empty2 <= UInt<1>("h0") @[MYFIFO.scala 86:24]
      else :
        node _T_5 = not(empty2) @[MYFIFO.scala 87:31]
        node _T_6 = and(empty3, _T_5) @[MYFIFO.scala 87:28]
        when _T_6 : @[MYFIFO.scala 87:39]
          buf3 <= buf2 @[MYFIFO.scala 88:22]
          empty3 <= UInt<1>("h0") @[MYFIFO.scala 89:24]
          empty2 <= UInt<1>("h1") @[MYFIFO.scala 90:24]
        else :
          node _T_7 = not(empty3) @[MYFIFO.scala 91:31]
          node _T_8 = and(empty4, _T_7) @[MYFIFO.scala 91:28]
          when _T_8 : @[MYFIFO.scala 91:39]
            buf4 <= buf3 @[MYFIFO.scala 92:22]
            empty4 <= UInt<1>("h0") @[MYFIFO.scala 93:24]
            empty3 <= UInt<1>("h1") @[MYFIFO.scala 94:24]
          else :
            when droptile : @[MYFIFO.scala 95:30]
              empty4 <= UInt<1>("h1") @[MYFIFO.scala 96:24]
              clearDrop <= UInt<1>("h1") @[MYFIFO.scala 97:27]
    node _io_ready_T = not(empty4) @[MYFIFO.scala 100:33]
    node _io_ready_T_1 = and(startup, _io_ready_T) @[MYFIFO.scala 100:29]
    node _io_ready_T_2 = not(droptile) @[MYFIFO.scala 100:46]
    node _io_ready_T_3 = and(_io_ready_T_1, _io_ready_T_2) @[MYFIFO.scala 100:42]
    io.ready <= _io_ready_T_3 @[MYFIFO.scala 100:18]
    io.full <= full @[MYFIFO.scala 101:17]
    io.tile <= buf4 @[MYFIFO.scala 102:17]

